1/8 ESDA6V1P6 ? january 2003 - ed: 2 quad transil? array for esd protection sot-666 where transient overvoltage protection in esd sensitive equipment is required, such as : n computers n printers n communication systems and cellular phones n video equipment this device is particularly adpated to the protection of symmetrical signals. main applications application specific discretes a.s.d. 1 3 2 6 5 4 functional diagram n 4 unidirectional transil? functions. n breakdown voltage v br = 6.1v min n low leakage current < 500 na n very small pcb area < 2.6 mm 2 features the ESDA6V1P6 is a monolithic array designed to protect up to 4 lines against esd transients. this device is ideal for applications where board space saving is required. description n high esd protection level. n high integration. n suitable for high density boards. benefits n iec61000-4-2 level 4: 15 kv (air discharge) 8 kv (contact discharge) n mil std 883e-method 3015-7: class 3 25kv hbm (human body model) complies with the following standards :
ESDA6V1P6 2/8 symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current a t voltage tempature coefficient v f forward voltage drop c capacitance per line r d dynamic resistance electrical characteristics (t amb = 25c) v i v cl v br v rm i f v f i rm i pp slope: 1/r d symbol parameter test conditions value unit v pp esd discharge - iec61000-4-2 air discharge iec61000-4-2 contact discharge 15 8 kv p pp peak pulse power (8/20 m s) (see note 1) t j initial = tamb 150 w t j junction temperature 125 c t stg storage temperature range -55to+150 c t l maximum lead temperature for soldering during 10s at 5mm for case 260 c t op operating temperature range -40to+150 c note 1: for a surge greater than the maximum values , the diode will fail in short-circuit. absolute ratings (t amb = 25c) types v br @i r i rm @v rm rd a tc min. max. max. typ. max. typ. @0v vvma m av w 10 -4 /c pf ESDA6V1P6 6.1 7.2 1 0.5 3 1.5 4.5 70 symbol parameter value unit r th(j-a) junction to ambient on printed circuit on recommended pad layout 220 c/w thermal resistances
ESDA6V1P6 3/8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 25 50 75 100 125 150 p [t initial] / p [t initial=25c) pp j pp j t (c) j fig. 1: relative variation of peak pulse power versus initial junction temperature. 10 100 1000 1 10 100 p (w) pp t (s) p t initial=25c j fig. 2: peak pulse power versus exponential pulse duration. 0.1 1.0 10.0 100.0 0 10203040506070 i (a) pp v (v) cl t =2.5s t initial=25c p j fig. 3: clamping voltage versus peak pulse current (typical values, rectangular waveform). 1.e-03 1.e-02 1.e-01 1.e+00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i (a) fm v (v) fm t =125c j t =25c j fig. 4: forward voltage drop versus peak forward current (typical values). 0 10 20 30 40 50 60 70 80 0123456 c(pf) v (v) r f=1mhz v =30mv t =25c osc rms j fig. 5: junction capacitance versus reverse voltage applied (typical values). 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 25 50 75 100 125 i [t ] / i [t =25c] rj rj v =3v r t (c) j fig. 6: relative variation of leakage current versus junction temperature (typical values).
ESDA6V1P6 4/8 technical information connector ic to be protected i/o2 i/o1 i/o4 i/o3 fig. a1: application example. with the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. electrostatic discharge (esd) is a major cause of failure in electronic systems. as a transient voltage suppressor, ESDA6V1P6 is an ideal choice for esd protection by suppressing esd events. it is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDA6V1P6. ESDA6V1P6 serves as a parallel protection elements, connected between the signal line and ground. as the transient rises above the operating voltage of the device, the ESDA6V1P6 becomes a low impedance path diverting the transient current to ground. 1. esd protection by ESDA6V1P6 the clamping voltage is given by the following formula: v cl =v br +r d .i pp as shown in figure a2, the esd strikes are clamped by the transient voltage suppressor. r d r g v g v br v(i/o) device to be protected esd surge esd6v1p6 i pp r load fig. a2: esd clamping behavior. to have a good approximation of the remaining voltages at both vi/o side, we provide the typical dynamical resistance value r d . by taking into account the following hypothesis: r g >r d and r load >r d we have: () vi o v r v r br d g g / =+ the results of the calculation done v g = 8kv, r g = 330 w (iec61000-4-2 standard), v br = 6.4v (typ.) and r d = 1.5 w (typ.) give: () v i o volts /. = 42 8 this confirms the very low remaining voltage across the device to be protected. it is also important to note that in this approximation the parasitic inductance effect was not taken into account. this could be a few tenths of volts during a few ns at the vi/o side.
ESDA6V1P6 5/8 15kv esd air discharge v(i/o) fig. a3: esd test board. gnd i/o1, i/o2, i/o3 or i/o4 v(i/o) 15kv esd air discharge fig. a4: esd test configuration. fig. a5: remaining voltage during esd surge. a: response in the positive way b: response in the negative way 2. crosstalk behavior r l1 r l2 ab 1g1 12g2 v+ v ab 2g2 21g1 v+ v line 1 line 2 v g1 v g2 drivers receivers r g1 r g2 fig. a6: crosstalk phenomenon
ESDA6V1P6 6/8 the crosstalk phenomena are due to the coupling between 2 lines. coupling factors ( b 12 or b 21 ) increase when the gap across lines decreases, particularly in silicon dice. in the example above, the expected signal on load r l2 is a 2 v g2 , in fact the real voltage at this point has got an extra value b 21 v g2 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k w ) v g gnd i/o1 i/o4 unloaded 50 w 50 w port 1 port 2 fig. a7: analog crosstalk test configuration. v g gnd i/o1 i/o4 unloaded 50 w 50 w port 1 port 2 fig. a8: typical analog crosstalk response. gnd i/o4 i/o1 v g1 b 21 g1 v unloaded unloaded pulse generator f= 100khz t = 20ns r 0 - 5v fig. a9: digital crosstalk test configuration. crosstalk b 21 g1 v fig. a10: typical digital crosstalk response.
ESDA6V1P6 7/8 3. pcb layout recommendations as esd is a fast event, the di/dt caused by this surge is about 30a/ns (risetime=1ns, ipeak=30a), that means each nh causes an overvoltage of 30v. thus, the circuit board layout is a critical design step in the suppression of esd induced transients by reducing parasitic inductances. to ensure that, the following guidelines are recommended : n the ESDA6V1P6 should be placed as close as possible to the input terminals or connectors. n the path length between the esd suppressor and the protected line should be minimized. n all conductive loops, including power and ground loops should be minimized. n the esd transient return path to ground should be kept as short as possible. n the connections from the ground pins to the ground plane should be the shortest possible. 4. comparison with varistors varistors transil? leakage current -- +++ protection efficiency -- ++ ageing -- ++ low leakage current for transil? device n improve the autonomy of portable equipments as mobile better efficiency in terms of esd protection by using transil? device n varistors are bidirectional devices and so are not suitable to protect sensitive ics, because they will be submitted to high voltages in the negative way. n ratio v cl /v br lower for transil? device n less dispersion in terms of v br no ageing phenomena regarding esd events with transil? device n higher efficiency in terms of esd protection esda 6v1 p6 esd array v min br package: sot-666 order code ordering type marking package weight base qty delivery mode ESDA6V1P6 b sot-666 2.9 mg. 3000 tape & reel
ESDA6V1P6 8/8 package mechanical data sot-666 d bp e1 e e lp he a u ref. dimensions millimeters inches min. max. min. max. a 0.50 0.60 0.020 0.024 bp 0.17 0.27 0.007 0.011 c 0.08 0.18 0.003 0.007 d 1.50 1.70 0.060 0.067 e 1.10 1.30 0.043 0.051 e 1.00 0.040 e1 0.50 0.020 he 1.50 1.70 0.059 0.067 lp 0.10 0.30 0.004 0.012 0.36 0.30 0.84 0.20 0.20 0.62 2.30 foot print (in millimeters) information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore spain - sweden - switzerland - united kingdom - united states. http://www.st.com
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